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Analog-to-digital converter (ADC) noise limits the dynamic range of many radio-frequency systems for test and measurement, sensor, and communications applications. Improvements in the total dynamic range (as measured by the SNR) can be achieved by combining M ADCs in parallel, yielding an increase in SNR of M if the noise is fully uncorrelated across ADC units. However, the presence of correlated noise will limit the SNR improvement to a factor less than M. Noise in an ADC is due to thermal processes, quantization, and clock jitter. In an array of ADCs, thermal and quantization noise are independently generated in each ADC, but if a common clock is used, its jitter will generate correlated sampling noise in all the ADCs in the array. In this paper, we analyze and experimentally measure the impact of previously proposed harmonic decorrelation techniques on the sampling noise of an array of parallel ADCs driven by a common clock, sampling at an intermediate frequency. Both theory and experiments reveal that the decorrelation techniques reduce the total sampling noise by half, which is a result that could substantially relax clock requirements for high-dynamic-range systems and thus reduce clock costs.