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High-speed ADC dynamic performance validation: The impact of skew-corner lot testing

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2 Author(s)
Seokjin Kim ; Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD ; Peckerar, Martin

Corner-lot process statistics have been demonstrated to provide important data on component yield and functionality. In this paper, we review the basics of this statistical approach and we show how they are applied to the dynamic performance of a high-speed (800 MS/s) dual channel 6-bit ADC. The skew-corner ADC performance test results allow us to determine (a) the quality the semiconductor fabricate process, (b) the sufficiency of the high speed ADC test and measurement equipment, and (c) which process parameters dominate yield.

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8-11 Sept. 2008