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Corner lot process variation effects on high speed ADCs for satellite receivers

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3 Author(s)
Seokjin Kim ; Univ. of Maryland, College Park ; Elkis, R. ; Peckerar, M.M.

In summary, we have demonstrated fully integrated high-speed ADC performance characteristics with process variations. The ADC corner lot study verified that process variations such from poly resistors and BJT-β and emitter area size can affect the ADC dynamic performance. The optimum ADC performances were achieved by setting the corner process as Lot 6 conditions which are maximum BJT-β and minimum BJT emitter area, while keeping the poly resistors values and without changing the ADC chip design.

Published in:

Semiconductor Device Research Symposium, 2007 International

Date of Conference:

12-14 Dec. 2007