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Accurate estimation of the effects of threshold variations, in particular yield loss, is crucial during the design of robust SRAM cells and memory arrays in deep submicron technologies. We present an efficient technique to calculate yield loss due to access-time, static noise margin, etc., related failures. Our method does not rely on Monte-Carlo techniques; instead, it finds the boundary in Vt (threshold voltage) parameter space between success and failure regions and uses quick geometrical calculations to find the yield. The Vt boundary curve is found efficiently via an Euler-Newton curve tracing technique, adapted from mixed-signal/RF simulation, that guides detailed SPICE-level simulation with accurate MOS device models. We compare and validate the new method against Monte-Carlo style yield estimation, obtaining superior accuracies and speedups of more than 10times.