Formal verification at higher levels of abstraction
Kroening, D.
Seshia, S.A.
Oxford Univ., Oxford;
This paper appears in: Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Publication Date: 4-8 Nov. 2007
On page(s): 572-578
Location: San Jose, CA,
ISSN: 1092-3152
ISBN: 978-1-4244-1382-9
INSPEC Accession Number: 9789825
Digital Object Identifier: 10.1109/ICCAD.2007.4397326
Current Version Published: 2007-12-10
Abstract
Most formal verification tools on the market convert a high-level register transfer level (RTL) design into a bit-level model. Algorithms that operate at the bit-level are unable to exploit the structure provided by the higher abstraction levels, and thus, are less scalable. This tutorial surveys recent advances in formal verification using high-level models. We present word-level verification with predicate abstraction and satisfiability modulo theories (SMT) solvers. We then describe techniques for term-level modeling and ways to combine word-level and term-level approaches for scalable verification.
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