http://ieeexplore.ieee.org TOC Alert for Publication# 4 2010 March 04 45 3 C1 C1 38 45 3 C2 C2 39 45 3 501 501 38 This paper presents a compact 0.18-$mu$m CMOS wideband gain-flattened low noise amplifier (LNA). The low noise characteristic of the LNA is achieved by the noise canceling technique and the gain flatness is enhanced by the gate-inductive gain-peaking technique. In addition to extending flat-gain bandwidth, the proposed gain-peaking technique results in better wideband noise canceling and quick gain roll-off outside the desired signal band to reject interference. Without using any passive inductor, the core size of the fully-integrated CMOS LNA circuit is only 145 $mu$ m$,times,$ 247 $mu$ m. The measured gain and noise figure of the CMOS LNA are 16.4 dB and 2.1 dB, respectively. The gain variation of the LNA is ${pm} $0.4 dB from 50 to 900 MHz. Operated at 1.8 V, the chip consumes 14.4 mW of power. ]]> 45 3 502 509 665 A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 $mu$ m CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT $Sigma Delta$ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of ${-}$ 30 dBm; the PLL phase noise is ${-}$110 dBc/Hz @$~$1 $~$MHz frequency offset with quadrature error less than 1$^{circ}$. ]]> 45 3 510 523 1595 A low power burst mode receiver architecture is presented which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A low power- and area-efficient clock recovery scheme uses the linear path to injection lock an oscillator. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is verified with experimental results at 5–10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. ]]> 45 3 524 537 3049 Supply voltage reduction with process scaling has made the design of analog, RF and mixed mode circuits increasingly difficult. In this paper, we present the design of an ultra-low voltage, low power and highly integrated dual-mode receiver for 2.4-GHz ISM-band applications. The receiver operates reliably from 0.55–0.65 V and is compatible with commercial standards such as Bluetooth and ZigBee. We discuss the design challenges at low voltage supplies such as limited f$_{rm T}$ for transistors and higher nonlinearities due to limited available signal swing, and present the architectural and circuit level design techniques used to overcome these challenges. The highly integrated receiver prototype chip contains RF front-end circuits, analog baseband circuits and the RF frequency synthesizer and was fabricated in a standard digital 90-nm CMOS process; it achieves a gain of 67 dB, noise figure of 16 dB, ${hbox{IIP}}_{3}$ of $-$10.5 dBm, synthesizer phase noise of $-$ 127 dBc/Hz at 3-MHz offset, consumes 32.5 mW from 0.6 V and occupies an active area of 1.7 ${hbox {mm}}^{2}$. ]]> 45 3 538 553 1400 A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13$,times,$ 0.41 mm$^{2}$ PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65$~$GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62$~$GHz; from 58 to 65$~$GHz, the measured PAE is above 10%. ]]> 45 3 554 564 1522 A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain–bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 $ mu{hbox {m}}$ CMOS technology and achieves a PSR better than $-$ 56$~$dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2$~$mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 $mu{hbox{A}}$ with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz. ]]> 45 3 565 577 1667 A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 $mu$s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1$~$mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90$~$ nm CMOS technology, the core area is only 0.352 mm $^{2}$. ]]> 45 3 578 586 1974 A low-power, reliable and re-configurable clock recovery circuit for UHF RFID transponders for the EPC Class-1 Generation-2 standard is proposed. Based on a digital frequency-locked loop, the clock recovery circuit uses timing information available in the downlink data, namely, the pulse intervals of the PIE-coded data, to calibrate an oscillator's output frequency to meet the stringent frequency accuracy requirement of the standard. Fabricated in a 0.18-$mu{hbox {m}}$ standard CMOS technology, the clock recovery circuit provides a calibrated frequency of 2.56 MHz with a frequency deviation within the range from $-$3.2% to $+ $1.2% over process, supply voltage and temperature variations. The chip has an active area of 0.22$~mu{hbox {m}}^{2}$, operates from a supply voltage from 0.75 V to 1.3 V, and consumes less than 2$~mu{hbox {W}}$ for a 1-V supply. ]]> 45 3 587 599 1674 This paper describes a time-domain temperature sensor based on a successive approximation algorithm. Without using any bipolar transistor, a temperature sensor composed of a temperature-dependent delay line (TDDL) is utilized to generate a delay proportional to the measured temperature. A binary-weighted adjustable reference delay line (ARDL) is adopted with an effective delay varied by a SAR control logic to approximate the TDDL delay for output coding. For linearity enhancement, a curvature compensation between both delay lines is invented to achieve the best ever accuracy among inverter-delay-based smart temperature sensors. With two-point calibration, a $-$0.4$,^{circ}{hbox{C}}$$,,sim,$ $+$0.6$,^{circ}{hbox{C}}$ inaccuracy (3$sigma$) over a 0$,^{circ}{hbox{C}}sim! {hbox {90}},^{circ}{hbox{C}}$ temperature operation range has been measured for 23 test chips. With 10 output bits, the proposed sensor achieves a resolution better than 0.1$,^{circ}{hbox{C}}$ and a chip area of 0.6 ${hbox {mm}}^{2}$ in a TSMC 0.35-$mu{hbox {m}}$ standard digital CMOS process. The sensor's average current consumption is 11.1 $mu{hbox{A}}$ at a conversion rate of 2$~$samp- les/s. ]]> 45 3 600 609 1476 A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-${hbox {mm}}^{2}$ ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a power consumption of 6.9 mW from a 1.0-V supply. ]]> 45 3 610 619 850 A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-digital converter (ADC) based on a fully differential class-AB switched operational amplifier achieves low power consumption with a differential input voltage of 2.4 Vp-p. A global-loop dynamic common-mode feedback circuit enables fully differential class-AB operation with dynamic current switching for power reduction. The prototype ADC shows a peak signal-to-noise-and-distortion ratio of 64.0 dB and a peak spurious-free dynamic range of 76.6 dB for a 31 MHz input signal at 50 MS/s while the measured differential and integral nonlinearities are within $pm $0.26 LSB and $pm $0.72 LSB, respectively. The prototype ADC in a 0.18 $mu{hbox {m}}$ 1P6M CMOS process consumes 18.4 mW at 50 MS/s and 1.8 V occupying an active die area of 0.26 ${hbox {mm}}^{2}$. ]]> 45 3 620 628 2270 A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described. A number of broadbanding and calibration techniques are used, which allow high-speed operation while consuming 80 mW from a 1 V supply. ESD protection is added to 40 Gb/s IOs and an inexpensive plastic package is used to make the chip closer to a commercial product. The measured tap delay frequency response variation is less than 1 dB up to 20 GHz and tap-to-tap delay variation is less than 0.3 ps. More than 50% vertical and 70% horizontal eye opening from a closed input eye are observed. The use of a CMOS process enables further integration of this core into a DFE equalizer or a CDR/Demux based receiver. ]]> 45 3 629 639 1038 Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge–Stone adders, ring oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide this data. Measurement data from the test-chips indicate that 1)$~$relative variation is significantly larger in low-voltage domains, 2) $~$within-die variation is spatially uncorrelated, and 3)$~$die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered. Lastly, extended analysis of the data reveals that systematic effects such as layout pattern dependencies or circuit structure can be misinterpreted as random but spatially-correlated variation. This suggests that circuit designers will reap more benefit from design tools capable of modeling systematic, position-dependent variation rather than spatially correlated, distance-dependent variation. ]]> 45 3 640 651 1766 In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the run-time ratio between different IPs. As a result, the minimum power consumption of the processor is only 15 mW, while the overall power consumption is 201 mW. As well as the reduction of power consumption, this work shows impressive performance improvement. The proposed fast modulo operators and adopted division-free algorithm reduces the critical latencies of 3-D display image processing. The proposed fast datapath with parallel architecture increase synthesis rate up to 116 fps which is 17 times faster than a previous work. In addition, reordered operation sequence fixes memory bandwidth regardless of the number of images to be produced. In the 3-D graphics IP and the decoding IP, redundant datapath are merged using an IEEE 754 compliant floating-point vector unit to save both chip area and power consumption, which even reduces the critical latency by 30%. ]]> 45 3 652 667 4940 We present a design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up to 100 MB/s suitable for digital consumer electronic applications. Our approach employs i) architecture-level parallelism to compensate throughput degradation, ii) a configurable $V_{rm T}$ balancer to mitigate the $V_{rm T}$ mismatch of nMOS and pMOS transistors operating in sub/near threshold, and iii) a fingered-structured parallel transistor that exploits $V_{rm T}$ mismatch to improve current drivability. Additionally, we describe the selection procedure of the standard cells and how they were modified for higher reliability in the subthreshold regime. All these concepts are demonstrated using SubJPEG, a $1.4times 1.4~{hbox {mm}}^{2}$ 65 nm CMOS standard- $V_{rm T}$ multi-standard JPEG co-processor. Measurement results of the discrete cosine transform (DCT) and quantization processing engines, operating in the subthreshold regime, show an energy dissipation of only 0.75 pJ per cycle with a supply voltage of 0.4 V at 2.5 MHz. This leads to $8.3times$ energy reduction when compared to using a 1.2 V nominal supply. In the near-threshold regime the energy dissipation is 1.0 pJ per cycle with a 0.45 V supply voltage at 4.5 MHz. The system throughput can meet 15 fps 640$,times,$480 pixel VGA standard. Our methodology is largely applicable to designing other sound/graphic and streaming processors. ]]> 45 3 668 680 3340 45 3 681 691 518 45 3 692 692 803 45 3 C3 C3 32 45 3 C4 C4 5