Using Implications for Online Error Detection
Nepal, K.; Alves, N.; Dworak, J.; Bahar, R.I.
Test Conference, 2008. ITC 2008. IEEE International
Volume , Issue , 28-30 Oct. 2008 Page(s):1 - 10
Digital Object Identifier   10.1109/TEST.2008.4700614
Summary:In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible - even with only a 10% area overhead.

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