An embedded processor based SOC test platform
Kuen-Jong Lee; Chia-Yi Chu; Yu-Ting Hong
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Volume , Issue , 23-26 May 2005 Page(s): 2983 - 2986 Vol. 3
Digital Object Identifier   10.1109/ISCAS.2005.1465254
Summary: In this paper, we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated test access mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.

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