Design of reconfigurable access wrappers for embedded core based SoC test
Koranne, S.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 11, Issue 5, Oct. 2003 Page(s): 955 - 960
Digital Object Identifier 10.1109/TVLSI.2003.817128
Summary:Testing of embedded core based system-on-chip (SoC) ICs is a well known problem, and the upcoming IEEE P1500 Standard on Embedded Core Test (SECT) standard proposes DFT solutions to alleviate it. One of the proposals is to provide every core in the SoC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a fixed test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers which allow for a dynamic change in the width of the TAM executing the core test. Analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Specifically, we derive a O(NC2B) time algorithm which can compute near optimal SoC test schedules, where NC is the number of cores and B is the number of top level TAMs. Experimental results on benchmark SoCs are presented which improve upon integer programming based methods, not only in the quality of the schedule, but also significantly reduce the computation time.
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