A P1500 compliant programmable BistShell for embedded memories
Koranne, S.; Wouters, C.; Waayers, T.; Kumar, S.; Beurze, R.; Visweswaran, G.S.
Memory Technology, Design and Testing, IEEE International Workshop on, 2001.
Volume , Issue , 2001 Page(s):21 - 27
Digital Object Identifier 10.1109/MTDT.2001.945224
Summary:We describe the design and implementation of an IEEE P1500
compliant programmable BIST for embedded memories. The proposed design
can be embedded in other cores or systems with minimum test generation
or test application overhead. The programmability of our BIST is useful
when the algorithm is being refined while the memory architecture is
under production. A variety of test algorithms can be implemented with
the programmability provided in our design with no change to the BIST
hardware. As an example we demonstrate the implementation of an
algorithm to detect open decoder faults. This example is shown for its
didactic content as it brings out the programmable axis of our design.
Our design also offers means to perform dedicated delay tests as well as
scan tests for diagnosis. We show by synthesis experiments that the
extra area cost for the BIST hardware is relatively small for medium to
large memories
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