Reducing Structural Bias in Technology Mapping
Satrajit Chatterjee; Alan Mishchenko; Robert K. Brayton; Xinning Wang; Timothy Kam
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 25, Issue 12, Dec. 2006 Page(s):2894 - 2903
Digital Object Identifier 10.1109/TCAD.2006.882484
Summary:Technology mapping, based on directed acyclic graph covering, suffers from the problem of structural bias: The structure of the mapped netlist depends strongly on the subject graph. In this paper, the authors present a new mapper aimed at mitigating structural bias. It is based on a simplified cut-based Boolean-matching algorithm, and using the speed afforded by this simplification, they explore two ideas to reduce structural bias. The first, called lossless synthesis, leverages recent advances in structure-based combinational-equivalence checking to combine the different networks seen during technology-independent synthesis into a single network with choices in a scalable manner. They show how cut-based mapping extends naturally to handle such networks with choices. The second idea is to combine several library gates into a single gate (called a supergate) in order to make the matching process less local. They show how supergates help address the structural-bias problem and how they fit naturally into the cut-based Boolean-matching scheme. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area, and run-time on academic and industrial benchmarks
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