A hierarchical test methodology for systems on chip
Jin-Fu Li; Hsin-Jung Huang; Jeng-Bin Chen; Chih-Pin Su; Cheng-Wen Wu; Chuang Cheng; Shao-I Chen; Chi-Yi Hwang; Hsiao-Ping Lin
Micro, IEEE
Volume 22, Issue 5, Sep/Oct 2002 Page(s): 69 - 81
Digital Object Identifier  
Summary:We present a hierarchical test methodology for testing a SOC with heterogeneous cores, including the 1149.1-wrapped, P1500-wrapped, and BIST memory cores. We propose an 1149.1-based hierarchical test manager that also provides P1500 test control signals. This scheme includes a memory BIST interface, providing both serial and parallel access ports for BIST circuits. Our approach offers low area and pin overhead, and high flexibility

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