Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips
Sehgal, A.; Goel, S.K.; Marinissen, E.J.; Chakrabarty, K.
Design, Automation and Test in Europe, 2006. DATE apos;06. Proceedings
Volume 1, Issue , 6-10 March 2006 Page(s):1 - 6
Digital Object Identifier   10.1109/DATE.2006.244140
Summary:Multiple levels of design hierarchy are common in current-generation system-on-chip (SOC) integrated circuits. However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider. In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator. Experimental results are presented for the ITC'02 SOC test benchmarks

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